Pei-Yu Lin 林珮玉

About Me

I’m a digital design engineer in training, with hands-on experience in RTL-to-GDSII flow, AI accelerator integration, and FPGA-based systems. My short-term goal is to become a digital design engineer. And my long-term aim is to 𝗹𝗲𝗮𝗱 𝗮 𝘁𝗲𝗮𝗺 𝘁𝗼 𝗺𝗮𝗸𝗲 𝘁𝗵𝗲 𝘄𝗼𝗿𝗹𝗱 𝗯𝗲𝘁𝘁𝗲𝗿.

Research & Internship Experience

• imec, Belgium (Upcoming 2025): RISC-V SoC integration of digital AI accelerators
• POSTECH, Korea (Summer 2025): NDP kernel design using SIMD on RISC-V Vector ISA
• RWTH Aachen (2024–2025): Research Assistant, FD-DAC tape-out, SPI system design
• FocalTech Systems (2023): SRAM controller & SPI protocol design on ASIC

Projects

• ASIP Design for SHA256 on trv32p3 (ASIP Designer)
• MazeRunner (UART, SPI, PID – ModelSim + DC Shell)
• Digital IC Design Projects (Virtuoso, 7nm PDK)
• NDP Kernel Optimization (Softmax, MLP, Histogram, SSSP)

Skills

• Programming: (System-)Verilog, C, C++, Python, TCL, Perl, MATLAB
• Tools: Cadence (Virtuoso, Xcelium, Innovus), Synopsys (DC, PrimeTime, ICC2), ModelSim, Questa, Vivado
• Concepts: RTL to GDSII, FPGA, AI accelerators, RISC-V, SoC integration, NDP, SIMD

Photography

• ...to be continue